The digital interface between radio frequency integrated circuits (RFICs) and baseband integrated circuits (BBIC) has to support increasingly high data rates with wireless communication standards such as the Third Generation Partnership Project (3GPP) Long Term Evolution (LTE) standard employing carrier aggregation. Digital interface standards are specified by the Mobile Industry Processor Interface (MIPI) Alliance. The current MIPI DigRF v4 draft interface requires a 5.2 GHz clock for transmitting data in the LTE 20+20+20 case, denoting aggregation of three 20 MHz portions of spectrum, rendering the physical implementation very challenging. These extremely high clock rates are required because the clock and data is transmitted with a single differential line. As an alternative, a three-wire interface is under consideration by the MIPI Alliance. This alternative interface uses three-level signals transmitted over three wires resulting in six unique states for data coding, so that theoretically log2(6) bits≈2.585 bits can be transmitted with three wires in one data transmission cycle. If the data is forced to change state every data transmission cycle, five unique states can be used to transfer theoretically log2(5) bits≈2.322 bits of data, while also a clock signal can be extracted from the changes in the transmitted signals. Furthermore, by permitting the data to change at both the rising and falling edges of a clock signal, a technique known as Double Data Rate (DDR), the data rate can be further doubled. However, the high bit rates required for the LTE carrier aggregation modes push the operating frequencies of the phase locked loop employed for clock synchronisation into the same range as employed by a frequency synthesiser incorporated in the RFIC. This means that the power consumption of the phase locked loop becomes comparable to the power consumption of the RFIC frequency synthesiser. Moreover, special radio frequency (RF) device modelling, and even special RF devices, such as varactors, are required to implement DigRF v4. In addition, known three-wire digital interfaces require a non-zero voltage difference between each pair of the wires.
The tri-state driver 10 illustrated in FIG. 1 may be used to drive a three-wire interface. The tri-state driver 10 comprises a NAND gate having a first input coupled to a first driver input EN and a second input coupled to a second driver input A. The tri-state driver 10 also comprises a NOR gate having a first input B coupled to the first driver input EN by means of an inverter INV and a second input coupled to the second driver input A. An output C of the NAND gate is coupled to a gate of a p-channel metal oxide semiconductor field effect transistor (MOSFET) Q2, and an output D of the NOR gate is coupled to a gate of an n-channel MOSFET Q1. A drain of the p-channel MOSFET Q2 and a drain of the n-channel MOSFET are coupled to an output OUT of the tri-state driver 10.
Also illustrated in FIG. 1 is a state table of the tri-state driver 10, showing for all combinations of binary values L and H applied to the first and second driver inputs EN, A, binary values at the first input B of the NOR gate, and at the outputs C, D of the NAND gate and NOR gate. The state table also indicates whether the p-channel MOSFET Q2 and the n-channel MOSFET Q1 are switched on or off. When the p-channel MOSFET Q2 is switched on and the n-channel MOSFET Q1 is switched off, the output OUT of the tri-state driver 10 has a binary value H, the tri-state driver 10 is sourcing current, and its output impedance is low. When the p-channel MOSFET Q2 is switched off and the n-channel MOSFET Q1 is switched on, the output OUT of the tri-state driver 10 has a binary value L, the tri-state driver 10 is sinking current, and, again, its output impedance is low. When the p-channel MOSFET Q2 and the n-channel MOSFET Q1 are both switched off, the output OUT of the tri-state driver 10 is floating and has a high impedance. Therefore, the impedance presented to a three-wire interface by the tri-state driver 10 is signal dependent, which can result in inter-symbol interference, particularly at high signalling speeds.
A known signalling system using a three-wire interface is illustrated in FIG. 2, and comprises a transmitter (TX) coupled to a receiver (RX) by means of three wires E, F, G. At the transmitter, each of the three wires E, F, G is coupled to two drivers by means of source resistors RS. At the receiver, each of the three wires E, F, G is terminated by a termination resistor RT, and comparators monitor voltage differences between pairs of the three wires E, F, G. The transmitter illustrated in FIG. 2 can provide line termination also for the high impedance state, when the transmitter is neither sourcing or sinking current over a particular wire, but such a transmitter can consume a significant amount of power which is not transmitted to the receiver.